From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from [87.239.111.99] (localhost [127.0.0.1]) by dev.tarantool.org (Postfix) with ESMTP id 7FAA3674158; Mon, 23 Oct 2023 12:54:50 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 dev.tarantool.org 7FAA3674158 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tarantool.org; s=dev; t=1698054890; bh=P5x+srJEHbrcQ2CD9XQN4sDMbxbqBQgaSZxkEWqFwsg=; h=Date:To:References:In-Reply-To:Subject:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=ZciT/CJwJDeybWaPRtrjaPLP+3QRl5k6chUazlqgfp3VHGNFEptU9V+j5N/3CmROw 9sJI7wototkdwZ5ocZFXm0RAmf8K2i6FrbLho6ljdlHzFvA0n7QZJsnJlBIoSFborQ ZqmNKTR8TMtPYDr/jpQoiIbcVuNCM2bFBVbWkgoI= Received: from smtpng1.i.mail.ru (smtpng1.i.mail.ru [94.100.181.251]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dev.tarantool.org (Postfix) with ESMTPS id 80D9466C07F for ; Mon, 23 Oct 2023 12:54:49 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 dev.tarantool.org 80D9466C07F Received: by smtpng1.m.smailru.net with esmtpa (envelope-from ) id 1qure4-0001Sh-AL; Mon, 23 Oct 2023 12:54:49 +0300 Date: Mon, 23 Oct 2023 12:50:19 +0300 To: Maxim Kokryashkin Message-ID: References: <2756cdf8d8a4be9aa55dfdadbd3453da067d8969.1697034851.git.skaplun@tarantool.org> <34475njdvtxhx3qirdoeqdyxxtc5gwcvx3j2az4e7s6dqgprnq@bb2ni5mj5ayw> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <34475njdvtxhx3qirdoeqdyxxtc5gwcvx3j2az4e7s6dqgprnq@bb2ni5mj5ayw> X-Mailru-Src: smtp X-4EC0790: 10 X-7564579A: B8F34718100C35BD X-77F55803: 4F1203BC0FB41BD9C197A170B57C5E43424B4CF9DFD4ED6F3F9F04D90C6DD02600894C459B0CD1B940F0BC02B69A2C506404D14D7C4900E7CFC77BF0D64D68567DF9FB97B487AEB4 X-7FA49CB5: FF5795518A3D127A4AD6D5ED66289B5278DA827A17800CE74BE895B46187343CEA1F7E6F0F101C67BD4B6F7A4D31EC0BCC500DACC3FED6E28638F802B75D45FF8AA50765F7900637BB46061768088B55EA1F7E6F0F101C6723150C8DA25C47586E58E00D9D99D84E1BDDB23E98D2D38BE5CCB53A13BC8DBA0C4F03D4AC5A89CD8EAEF0E668A53141CC7F00164DA146DAFE8445B8C89999728AA50765F7900637D0FEED2715E18529389733CBF5DBD5E9C8A9BA7A39EFB766F5D81C698A659EA7CC7F00164DA146DA9985D098DBDEAEC8989FD0BDF65E50FBF6B57BC7E6449061A352F6E88A58FB86F5D81C698A659EA7E827F84554CEF5019E625A9149C048EE33AC447995A7AD182315B90ADEC130413A03B725D353964B2FFDA4F57982C5F435872C767BF85DA227C277FBC8AE2E8BECD345639C7F4A9E75ECD9A6C639B01B4E70A05D1297E1BBCB5012B2E24CD356 X-C1DE0DAB: 0D63561A33F958A55A4E123F1C86FEFF9F11958FD825B16F86A7892DA55F802AF87CCE6106E1FC07E67D4AC08A07B9B064E7220B7C550592CB5012B2E24CD356 X-C8649E89: 1C3962B70DF3F0ADE00A9FD3E00BEEDF3FED46C3ACD6F73ED3581295AF09D3DF87807E0823442EA2ED31085941D9CD0AF7F820E7B07EA4CF67176501213830E28C2CC625AF2AFC9F66FC5BF1F039DA6D5779D8949986350FE781F4E203C57078A8B50B9382ADB12AF9F58FD8EF18E0694251C9DBF537AA37E48CAC7CA610320002C26D483E81D6BE5EF9655DD6DEA7D65774BB76CC95456EEC5B5AD62611EEC62B5AFB4261A09AF0 X-D57D3AED: 3ZO7eAau8CL7WIMRKs4sN3D3tLDjz0dLbV79QFUyzQ2Ujvy7cMT6pYYqY16iZVKkSc3dCLJ7zSJH7+u4VD18S7Vl4ZUrpaVfd2+vE6kuoey4m4VkSEu530nj6fImhcD4MUrOEAnl0W826KZ9Q+tr5ycPtXkTV4k65bRjmOUUP8cvGozZ33TWg5HZplvhhXbhDGzqmQDTd6OAevLeAnq3Ra9uf7zvY2zzsIhlcp/Y7m53TZgf2aB4JOg4gkr2biojqlVu258LHAE4N4rYYLSkiA== X-DA7885C5: 358D28AA66A9E0A17E8C13BDE826CD8DE036B0B3AE49B5F4AF24D21E4572C84E262E2D401490A4A0DB037EFA58388B346E8BC1A9835FDE71 X-Mailru-Sender: 689FA8AB762F73930F533AC2B33E986B807C0E62DCFB37F5197856955ABB7A5D0FBE9A32752B8C9C2AA642CC12EC09F1FB559BB5D741EB962F61BD320559CF1EFD657A8799238ED55FEEDEB644C299C0ED14614B50AE0675 X-Mras: Ok Subject: Re: [Tarantool-patches] [PATCH luajit 2/2] Fix base register coalescing in side trace. X-BeenThere: tarantool-patches@dev.tarantool.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Tarantool development patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Sergey Kaplun via Tarantool-patches Reply-To: Sergey Kaplun Cc: tarantool-patches@dev.tarantool.org Errors-To: tarantool-patches-bounces@dev.tarantool.org Sender: "Tarantool-patches" Hi, Maxim! Thanks for the review! Fixed your comments and force-pushed the branch! On 13.10.23, Maxim Kokryashkin wrote: > Hi, Sergey! > Thanks for the patch! > LGTM, except for a few comments below. > > On Wed, Oct 11, 2023 at 06:04:10PM +0300, Sergey Kaplun wrote: > > From: Mike Pall > > > > Thanks to Sergey Kaplun, NiLuJe and Peter Cawley. > > > > (cherry-picked from commit aa2db7ebd1267836af5221336ccb4e9b4aa8372d) > > > > The previous patch fixed just part of the problem with the register > > coalesing. For example, the parent base register may be used inside the > > parent or child register sets when it shouldn't. This leads to incorrect > > register allocations, which may lead to crashes or undefined behaviour. > > This patch fixes it by excluding the parent base register from both > > register sets. > > > > The test case for this patch doesn't fail before the commit since it > > requires specific register allocation, which is hard to construct and > > very fragile. Due to the lack of ideal sync with the upstream > > repository, the test is passed before the patch. > > It should become correct in future patches. > Typo: s/in future patches/after backporting future patches/ Fixed, thanks! > > > > Resolves tarantool/tarantool#8767 > How can I reassure that, since we don't have any reproducer? You may try the recipe mentioned in the ticket and see that there are no any crashes anymore. > > diff --git a/test/tarantool-tests/lj-1031-asm-head-side-base-reg.test.lua b/test/tarantool-tests/lj-1031-asm-head-side-base-reg.test.lua > > new file mode 100644 > > index 00000000..fc5efaaa > > --- /dev/null > > +++ b/test/tarantool-tests/lj-1031-asm-head-side-base-reg.test.lua > > @@ -0,0 +1,139 @@ > > +local tap = require('tap') > > +-- Test file to demonstrate incorrect side trace head assembling > > +-- when use parent trace register holding base (`RID_BASE`). > > +-- See also, https://github.com/LuaJIT/LuaJIT/issues/1031. > > +-- > > +-- XXX: For now, the test doesn't fail even on arm64 due to the > > +-- different from upstream register allocation. Nevertheless, this > > +-- issue should be gone with future backporting, so just leave the > > +-- test case as is. > > +local test = tap.test('lj-1031-asm-head-side-base-reg'):skipcond({ > > + ['Test requires JIT enabled'] = not jit.status(), > > +}) > > + > > +local ffi = require 'ffi' > Please use parantheses here too. Fixed, thanks! > > +local int64_t = ffi.typeof('int64_t') > > + > > + > > +local ARR_SIZE = 1e2 > Maybe it is better to just write it as 100? Fixed. > > +local lim_arr = {} > > + > > +-- XXX: Prevent irrelevant output in jit.dump(). > > +jit.off() > > + > > +local INNER_TRACE_LIMIT = 20 > > +local INNER_LIMIT1 = 1 > > +local INNER_LIMIT2 = 4 > Please drop a comment with explanation of why those numbers were chosen. Added, see the full patch below. > > +for i = 1, INNER_TRACE_LIMIT do lim_arr[i] = INNER_LIMIT1 end > > +for i = INNER_TRACE_LIMIT + 1, ARR_SIZE + 1 do lim_arr[i] = INNER_LIMIT2 end > These loops are hardly readable, it would be nice to make the multiline. Fixed. > > + > > + if k > 55 then else end > Please drop a comment and explain why it is 55, for some people > that is not obvious. Added. See iterational patch below. Brach is force-pushed. =================================================================== diff --git a/test/tarantool-tests/lj-1031-asm-head-side-base-reg.test.lua b/test/tarantool-tests/lj-1031-asm-head-side-base-reg.test.lua index fc5efaaa..35364f4e 100644 --- a/test/tarantool-tests/lj-1031-asm-head-side-base-reg.test.lua +++ b/test/tarantool-tests/lj-1031-asm-head-side-base-reg.test.lua @@ -11,7 +11,7 @@ local test = tap.test('lj-1031-asm-head-side-base-reg'):skipcond({ ['Test requires JIT enabled'] = not jit.status(), }) -local ffi = require 'ffi' +local ffi = require('ffi') local int64_t = ffi.typeof('int64_t') test:plan(1) @@ -60,21 +60,31 @@ local r17 local r18 local r19 -local ARR_SIZE = 1e2 +local ARR_SIZE = 100 local lim_arr = {} -- XXX: Prevent irrelevant output in jit.dump(). jit.off() +-- `INNER_LIMIT1` - no cycle is taken. +-- `INNER_LIMIT2` - cycle is taken and compiled. +-- `INNER_TRACE_LIMIT` - empirical number of iterations to compile +-- all necessary traces from the outer cycle. local INNER_TRACE_LIMIT = 20 local INNER_LIMIT1 = 1 local INNER_LIMIT2 = 4 -for i = 1, INNER_TRACE_LIMIT do lim_arr[i] = INNER_LIMIT1 end -for i = INNER_TRACE_LIMIT + 1, ARR_SIZE + 1 do lim_arr[i] = INNER_LIMIT2 end +for i = 1, INNER_TRACE_LIMIT do + lim_arr[i] = INNER_LIMIT1 +end +for i = INNER_TRACE_LIMIT + 1, ARR_SIZE + 1 do + lim_arr[i] = INNER_LIMIT2 +end -- Enable compilation back. jit.on() +-- XXX: `hotexit` is set to 2 to decrease the number of +-- meaningless side traces. jit.opt.start('hotloop=1', 'hotexit=2') -- XXX: Trace numbers are given with the respect of using @@ -105,6 +115,8 @@ while k < ARR_SIZE do local l19 = ffi_new(int64_t, k + 19) -- Side exit for TRACE 6 start 2/1. -- luacheck: ignore + -- XXX: The number is meaningless, just needs to be big enough + -- to be sure that all necessary traces are compiled. if k > 55 then else end r1 = tonumber(l1) r2 = tonumber(l2) =================================================================== > > -- Best regards, Sergey Kaplun