From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp46.i.mail.ru (smtp46.i.mail.ru [94.100.177.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dev.tarantool.org (Postfix) with ESMTPS id A7477469719 for ; Thu, 15 Oct 2020 11:41:56 +0300 (MSK) Date: Thu, 15 Oct 2020 11:41:55 +0300 From: Kirill Yukhin Message-ID: <20201015084155.vllfcrzbmvsnqm5l@tarantool.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Subject: Re: [Tarantool-patches] [PATCH] jit: fix cdatanum addressing for GC64 mode on x86 List-Id: Tarantool development patches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Munkin Cc: tarantool-patches@dev.tarantool.org Hello, On 14 окт 16:53, Igor Munkin wrote: > This patch fixes the regression introduced in scope of > 5f6775ae0e141422193ad9b492806834064027ca ('core: introduce various > platform metrics'). As a result of the patch displacement is > misencoded when GC64 mode is enabled. > > In X86 long mode 32-bit displacement is encoded either via SIB byte or > is addressed relatively to RIP register value. The first approach is > used in JIT for 32-bit addresses (i.e. when GC64 mode is disabled), but > doesn't work for 64-bit ones. As a result all addresses to GG_State > contents to be "hardcoded" on the trace are encoded relatively to > RID_DISPATCH register (i.e. callee-safe R14 register) containing global > dispatch table. For this purpose this register is not used by the JIT > register allocator in GC64 build and not spoiled throughout LuaJIT VM > cycle (and therefore trace execution). > > NB: Since R14 is the additional GRP, the instruction ought to be > REX-prefixed. > > Follows up tarantool/tarantool#5187 > > Reported-by: Vladislav Shpilevoy > Signed-off-by: Igor Munkin I've checked your patch into 1.10, 2.4, 2.5 and master. -- Regards, Kirill Yukhin